发明名称 DEBUGGING CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND DEBUGGING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten time required for debugging a semiconductor integrated circuit, which has a plurality of functional circuits inside and to which only a small number of pins for debugging allocated. SOLUTION: The debugging efficiency of the semiconductor integrated circuit is enhanced by providing a flexible scheduler 10 by which scheduling is performed according to debugging use in the semiconductor integrated circuit 100. In addition, further enhancement of the debugging efficiency is possible by storing traces of an internal signal in an internal memory separately from a signal to be outputted to the outside of the semiconductor integrated circuit.
申请公布号 JP2003044315(A) 申请公布日期 2003.02.14
申请号 JP20010231879 申请日期 2001.07.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TANAKA TAKATOSHI;ARAKI TOSHIYUKI
分类号 G06F11/22;G06F15/78;H01L21/822;H01L27/04 主分类号 G06F11/22
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