| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the time of for the overall write operation cycle, including reading and erasure, and enhance affinity with a CMOS process for facilitating realization of a low-cost memory hybrid system LSI. SOLUTION: The memory has channel-sharing MIS transistors and memory transistors, having a gate dielectric film GD1 composed of a plurality of laminated dielectrics, including charge-storing means dispersed therein. At writing, hot electrons HE generated near the boundary of the MIS transistor and the memory transistor are injected into the gate dielectric film GD1 from the source S side thereof (Fig. 8A). At erasing, hot holes HH1, HH2 generated at the drain D side are injected in a distribution region of electrons stored in the gate dielectric film GD1 from the drain D side (Fig. 8B).</p> |
