| 摘要 |
PROBLEM TO BE SOLVED: To provide an address generating circuit to execute address generation by modulo addition at high speed. SOLUTION: In the address generating circuit, a 2-input adder 101 that adds an address DP 105 and an update step DN 106, a 3-input adder-subtractor 102 that performs addition and subtraction of the DP 105, the DN 106 and modulo objective area size DM 107 and a selection judging circuit 103 that generates a selection signal to select one of output results of the adder-subtractors 101, 102 are independently operated in parallel and the output results of the adder 101 and the adder-subtractor 102 are selected based on the selection signal from the selection judging circuit 103 by a multiplexer 104.
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