发明名称 TIMER CONTROL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a timer control circuit where each timer can optionally be in cascade connection and the optional timers can build up cascade connection timers and to suppress increase in the circuit scale by effectively utilizing the timers. SOLUTION: A software program controls a value of a cascade connection selection control register 90 and a cascade connection changeover control circuit 80 can control cascade connection of optional timers among a plurality of timers according to the value of the cascade connection selection control register 90. Thus, an optional timer configuration can be built up and existing timers can effectively be utilized, then the increase in the circuit scale can be suppressed.
申请公布号 JP2003046381(A) 申请公布日期 2003.02.14
申请号 JP20010235648 申请日期 2001.08.03
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HOSOI DAISUKE
分类号 H03K17/28;(IPC1-7):H03K17/28 主分类号 H03K17/28
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