| 摘要 |
PROBLEM TO BE SOLVED: To provide a flip-flop circuit capable of high-speed operation that can reduce a signal propagation delay time from a switching of a clock signal until its output even for the presence of unsharpened waveform. SOLUTION: A data signal received at a data input terminal 1 is given to a closed loop comprising an inverter 10 and a clocked inverter 8 via a clocked inverter 7 and given further to a data transfer element via an inverter 11. An output side of the data transfer element comprising a parallel connection circuit of a P-channel data transfer gate 4 and N-channel data transfer gates 5, 6 is connected to a closed loop comprising an inverter 13 and a clocked inverter 9 and connected to a data output terminal 3 via an inverter 12. An inverted clock signal CB by an inverter 14 or a noninverting clock signal C by inverters 14, 15 is given to each clocked inverter and each data transfer gate.
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