| 摘要 |
This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular block after a failure is detected in the block. In the test system which tests writing and erasing as a unit of block in the memory under test by using a match function includes a register (61) provided for each memory under test (MUTn) for holding a first failure generated in a particular block at a first control signal (Ca) from a pattern generator (2), establishes a match condition, a pass condition, and a write inhibit condition for the particular block for test cycles after the first failure; and resets the register at a cycle specified by a second control signal (Cb) from the pattern generator to release the match condition, pass condition, and write inhibit condition.
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