INTEGRATED SEMICONDUCTOR MEMORY ARRANGEMENT AND A METHOD FOR PRODUCING THE SAME

摘要

The invention relates to a method for producing an integrated semiconductor memory arrangement. According to said method, two capacitor modules (10, 20) are formed for each selection transistor (8) from the front and rear side of the substrate wafer (1) respectively. Said inventive process achieves a higher packing density of memory cells by the utilisation of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to "0" or "1" can also be saved for each selection transistor (8) in a ferroelectric memory arrangement, if the two capacitor modules have a different structure in terms of layer thickness, surface area or material.