发明名称 |
MRAM BIT LINE WORD LINE ARCHITECTURE |
摘要 |
A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the cross-points in the array. A bit decoder and word decoder are coupled to the bit lines and word lines, respectively. A first series of switch circuits are coupled to and located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines such that a shortened programming current path is provided which results in decreased resistance across the device. |
申请公布号 |
WO02059899(A3) |
申请公布日期 |
2003.02.13 |
申请号 |
WO2002US01925 |
申请日期 |
2002.01.24 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
发明人 |
VIEHMANN, HANS-HEINRICH |
分类号 |
G11C11/15;G11C7/12;G11C7/18;G11C8/08;G11C8/14;G11C11/16;H01L21/8246;H01L27/105 |
主分类号 |
G11C11/15 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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