发明名称 Clock switching circuitry for avoiding conflict of data handling occuring in a memory
摘要 Clock switching circuitry includes a memory having a plurality of storage locations of a particular address each and configured to allow data to be written in and read out at the same time. The circuitry further includes a write pointer, a read pointer, a synchronizing circuit, a conflict detector, and a conflict avoiding circuit. The circuitry detects a conflict with high reliability and facilitates design using a CAD (Computer Aided Design) tool.
申请公布号 US2003031080(A1) 申请公布日期 2003.02.13
申请号 US20020103844 申请日期 2002.03.25
申请人 ARATA YUICHI;KIMURA NAOYA;ODAGIRI HIDEAKI 发明人 ARATA YUICHI;KIMURA NAOYA;ODAGIRI HIDEAKI
分类号 H04L7/00;G11C7/10;G11C8/18;(IPC1-7):G11C8/00 主分类号 H04L7/00
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