| 摘要 |
A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region. An alternative JOI structure and cell layout of the present invention includes at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate containing at least a conductive region other than source/drain diffusion regions present atop an insulating layer embedded therein, said insulating layer not being present beneath said at least one patterned gate stack region, wherein said conductive region is in contact with vertical sidewalls of source/drain extension regions present in said semiconductor substrate, beneath said at least one patterned gate stack region.
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