发明名称 Method of fabricating a wafer level package
摘要 A fabrication method of wafer level packages capable of improving reliability by maximizing a contact area of metal wiring and a conductive ball and of simplifying fabrication processes by reducing the number of sputtering. The disclosed method comprises the steps of: providing a substrate having a plurality of chip pads on the upper part thereof; forming a first insulating layer including a first opening exposing the chip pad and a second opening forming a ball land on the substrate; forming metal wiring connected to the chip pad in a single unit through the first opening and covering the second opening to have a ball land on the first insulating layer; forming a second insulating layer including a third opening which covers the metal wiring, however, exposes the ball land; and adhering a conductive ball to be in contact with the third opening on the ball land.
申请公布号 US2003032276(A1) 申请公布日期 2003.02.13
申请号 US20010024892 申请日期 2001.12.18
申请人 KIM JONG HEON 发明人 KIM JONG HEON
分类号 H01L23/48;H01L21/60;H01L23/31;H01L23/485;(IPC1-7):H01L21/44;H01L21/48;H01L21/50 主分类号 H01L23/48
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