发明名称 |
Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation |
摘要 |
A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.
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申请公布号 |
US2003032261(A1) |
申请公布日期 |
2003.02.13 |
申请号 |
US20010924903 |
申请日期 |
2001.08.08 |
申请人 |
YEH LING-YEN;LOU CHINE-GIE |
发明人 |
YEH LING-YEN;LOU CHINE-GIE |
分类号 |
H01L21/762;H01L21/8234;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/762 |
代理机构 |
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地址 |
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