| 摘要 |
A memory core with an access time that does not include a delay associated with decoding address information. Address decode logic is removed from the memory core and the address decode operation is performed in an addressing pipeline stage that occurs during a clock cycle prior to a clock cycle associated with a memory access operation for the decoded address. After decoding the address in a first pipeline stage, the external decode logic drives word lines connected to the memory core in a subsequent pipeline stage. Since the core is being driven by word lines, the appropriate memory locations are accessed without decoding the address information within the core. Thus, the delay associated with decoding the address information is removed from the access time of the memory core.
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