REGISTER, MEMORY MODULE AND MEMORY SYSTEM

摘要

PURPOSE: To provide a register capable of coping with a wide frequency range and without depending on the number of mounted devices. CONSTITUTION: First and second preprocessing flip-flop FF1a and FF1b latch a C/A signal (CAint) inputted in a register 40a with a clock (0.5WCLKint) having a frequency of a half of that of an external clock signal WCLK and its inversion clock. Thus, the C/A signal is temporarily extended to a set of signals (0.5CA-a and 0.5CA-b) having double cycle. Since the signals 0.5CA-a and 0.5CA-b have the double cycle of that of the C/A signal (CAint), first and second post-processing flip-flops FF2a and FF2b can perform the latch operations according to an internal clock signal intCLK generated by a DLL circuit in a state that the sufficient setup time and hold time are secured.