发明名称 |
System and method for reducing timing mismatch in sample and hold circuits using the clock |
摘要 |
The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises synchronizing a hold signal to a clock signal by modifying the hold signal for each of a plurality of sample and hold subcircuits within the sample and hold circuit and utilizing the modified hold signals in the sample and hold subcircuits, respectively.
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申请公布号 |
US6518800(B2) |
申请公布日期 |
2003.02.11 |
申请号 |
US20010866273 |
申请日期 |
2001.05.25 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MARTIN DAVID A.;SPAETH MARK C. |
分类号 |
G11C27/02;H03M1/10;H03M1/12;(IPC1-7):H03K17/00 |
主分类号 |
G11C27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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