Circuit and method for controlling buffers in semiconductor memory device

摘要

Disclosed inventions include circuits and methods for controlling a plurality of data input buffers and a plurality data strobe buffers in a semiconductor memory device. High speed operation can be achieved by operating the plurality of data input buffers and the plurality of data strobe buffers in response to a buffer control signal generated faster than an input data, synchronized with internal rising and falling clock signals. A first internal falling clock signal generator generates a first internal falling clock signal in response to an external clock signal. A first internal rising clock signal generator generates a first internal rising clock signal in response to the external clock signal. A buffer controller generates a buffer control signal in response to the first and falling and rising clock signals. The plurality of data input buffers and the plurality of data strobe buffer are enabled or disabled in response to the buffer control signal.