发明名称 PLL frequency synthesizer circuit
摘要 A voltage-controlled oscillator outputs a signal of a frequency controlled by a voltage of an input signal, the output signal being used for feedback as an internal change signal. A phase comparator detects a phase difference between the internal change signal and an external reference signal. A charge pump outputs the signal having the voltage based on the phase difference to the voltage-controlled oscillator via a low-pass filter. The charge pump is controlled so that the voltage of the signal input to voltage-controlled oscillator becomes a voltage for oscillating a lock frequency. When instruction of changing the lock frequency is input, and/or a phase inversion of the internal change signal used for feedback in a locking-up operation rendered in response to the instructions is detected, a control is made such that an absolute value of an output current of the charge pump is increased.
申请公布号 US6518845(B2) 申请公布日期 2003.02.11
申请号 US20010809221 申请日期 2001.03.16
申请人 FUJITSU LIMITED 发明人 NAKAMICHI HIROTO
分类号 H03L7/089;H03L7/093;H03L7/107;H03L7/183;(IPC1-7):H03L7/00 主分类号 H03L7/089
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