发明名称 |
Current leakage reduction for loaded bit-lines in on-chip memory structures |
摘要 |
Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
|
申请公布号 |
US6519178(B2) |
申请公布日期 |
2003.02.11 |
申请号 |
US20020172107 |
申请日期 |
2002.06.13 |
申请人 |
INTEL CORPORATION |
发明人 |
ALVANDPOUR ATILA;KRISHNAMURTHY RAM K.;NARENDRA SIVA G. |
分类号 |
G11C11/412;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/412 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|