发明名称 |
Read data valid loop-back for high speed synchronized DRAM controller |
摘要 |
In a synchronized memory system comprising a memory controller externally coupled to a synchronous memory, a read valid loop back signal is introduced for the memory controller to track the delays of signals exchanged between the memory controller and the synchronous memory, so that the uncertainty introduced by I/O pads and PCB traces used to facilitate the coupling of the memory controller with the sychronous memory is no longer the limiting factor for the speed of the memory controller. An asynchronous FIFO buffer is used to latch read data returned by the synchronous memory based on the read valid loop back signal.
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申请公布号 |
US6519688(B1) |
申请公布日期 |
2003.02.11 |
申请号 |
US20000676460 |
申请日期 |
2000.09.29 |
申请人 |
S3 INCORPORATED |
发明人 |
LU WEI G.;NAYAK BIRANCHI N. |
分类号 |
G06F13/16;G11C7/10;(IPC1-7):G06F12/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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