| 摘要 |
PURPOSE: A digitally controlled analog delay locked loop is provided to be capable of obtaining fine resolution, fast lock acquisition, wide locking range, and lower speed sorts that have the same resolution as higher speed sorts. CONSTITUTION: A digitally controlled analog DLL(delay locked loop)(100) includes an input(102) that receives a reference clock(e.g., REF_CLK) and an output(104) that presents a signal(e.g., CLK_OUT). The circuit(100) is configured to generate the signal(CLK_OUT) having an edge(e.g., rising or falling) that precedes a corresponding edge of the signal(REF_CLK) by a predetermined period of time. The signal(CLK_OUT) tracks the jitter and duty cycle of the signal(REF_CLK). |
