发明名称 Capacitive alignment structure and method for chip stacking
摘要 An alignment structure (14) and method for aligning a first circuit image region (18) of a microelectronic chip (10) with a second circuit region (20) of a wafer (12). The alignment structure comprises a plurality of passive coupling elements (22) attached to the chip and arranged in a linear array and further comprises a plurality of electrodes (24) attached to the wafer and arranged in a linear array. The electrodes are arranged into a set of first driven electrodes (46), a set of second driven electrodes (48) and a set of sensing electrodes (50). The first driven, second driven and sensing electrodes are arranged alternatingly with one another and may each include one or more plates (62). The first and second driven electrodes are driven, respectively, with sine wave signals 180 degrees out of phase with one another. When each passive coupling element is centered over a corresponding sensing electrode, the signals from all of the sensing electrodes are null, indicating that the first circuit image region is aligned with the second circuit image region in the alignment direction. In an alternative embodiment, individual electrodes are configurable into different size first driven, second driven and sensing electrodes to adjust the alignment resolution of the alignment structure.
申请公布号 US6518679(B2) 申请公布日期 2003.02.11
申请号 US20000738167 申请日期 2000.12.15
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LU NING;PRICER WILBUR DAVID;WHITING CHARLES ARTHUR
分类号 G06K9/00;H01L21/98;H01L23/48;H01L23/544;H01L25/065;(IPC1-7):H01L23/544 主分类号 G06K9/00
代理机构 代理人
主权项
地址