Process for reducing critical dimensions of contact holes, vias, and trench structures in integrated circuits

摘要

An integrated circuit fabrication process to pattern reduced feature size is disclosed herein. The process includes reducing the width of a patterned area of a patterned photoresist layer provided over a substrate before patterning the substrate. The patterned area is representative of a feature to be formed in the substrate. The width of the feature is reduced by an electron beam mediated heating and flowing of select areas of the patterned photoresist layer.