| 摘要 |
In one embodiment, a circuit element is described in text representation in a HDL source code file. The text representation is provided to a synthesis compiler for compilation. The text representation contains multiple expressions describing the logic circuits. During synthesis compilation, object names are selected for each expression in the text representation. The object names are derived from local counters and from the expressions depending on the context of the expressions such that a revision of one section of the source HDL text only affects the object names of the expressions local to the revised section. The object names of other sections of the source HDL text are not affected and remain the same.
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