发明名称 Software programmable delay circuit
摘要 A phase adjustment circuit has a signal path having a plurality of phase adjustment elements coupled together. Each of the phase adjustment elements of the plurality has a first path and a second path. The second path of each of the phase adjustment elements of the plurality adds a smaller amount of phase adjustment to the signal path than the first path of each of the phase adjustment elements of the plurality. The amount of phase adjustment added by each of the phase adjustment elements of the plurality is cumulative. The phase adjustment circuit also has a selection circuit coupled to each of the phase adjustment elements of the plurality to provide selection of either the first path or the second path of each of the phase adjustment elements of the plurality.
申请公布号 US6518811(B1) 申请公布日期 2003.02.11
申请号 US20000752367 申请日期 2000.12.29
申请人 CISCO TECHNOLOGY, INC. 发明人 KLECKA, III RUDOLPH B.
分类号 H03H17/08;(IPC1-7):H03H11/26 主分类号 H03H17/08
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