| 摘要 |
A clock generating circuit 10, for generating a clock signal of which frequency is variable, has a delay circuit 20, a selector 30 and a control circuit 40. The delay circuit 20 has buffers 21 to 24 for delaying the input clock signal and output terminals 30A to 30D each of which outputs a clock signal delayed by a different delay time. The selector 30 selects one of the output terminals in the delay circuit 20, based on the output from the control circuit 40. The control circuit 40 supplies an output signal formed of a group of bits that is circulated in a predetermined cycle, to the selector 30. A cycle in an output clock signals OUT sequentially outputted from the output terminal 12 through the output terminals selected by the selector 30 increases or decreases in accordance with the group of bits in the output signal. Thus, the frequency in the output clock signal OUT will vary to reduce EMI noise.
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