发明名称 DATA TRANSFER CONTROLLER FOR FIFO MEMORY
摘要 PROBLEM TO BE SOLVED: To actualize less power consumption and faster data transfer when the same data are successively transferred. SOLUTION: When data which are as much as the capacity of an area A are written, an in-area data coincidence detection part 7 decides whether the data written to the area A are all the same. When so, the detection part 7 sets a bit in an area register 9 which corresponds to the area A to '1', but when not, the bit is set to '0'. When data in an object area 6 are all the same, a FIFO memory 5 outputs one word only once from the head address of the area 6 having the same data and sets it in an ATA/ATAPI data register 2. Then the supply of a readout-side clock is stopped.
申请公布号 JP2003036145(A) 申请公布日期 2003.02.07
申请号 JP20010223177 申请日期 2001.07.24
申请人 SHARP CORP 发明人 IIJIMA YASUTAKA
分类号 G06F3/06;G06F13/38;(IPC1-7):G06F3/06 主分类号 G06F3/06
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