| 摘要 |
PURPOSE: A twin MONOS array metal bit organization and a single cell operation are provided to address a memory cell as a function of the word line, bit line and control gate of the twin MONOS metal bit line memory array. CONSTITUTION: An addressing method for a twin MONOS metal bit line array includes the steps of: (a) labeling word lines(WL£0|,WL£1|) from a low word line address to a high word line address;(b) labeling control gate lines(CG£0|,CG£1|,CG£2|) from a low control gate address to a high control gate address; (c) labeling bit lines(BL_E£0|,BL_E£1|,BL_E£2|) from a low bit line address number to a high bit line address number with an additional designation as "even" and "odd" for each the address number; (d) selecting a set of three dimensional addresses "X", "Y" and "Z"; (e) selecting the word line address as the "X" address; (f) selecting the control gate address as a function of the "X" and the "Z" addresses; and (g) selecting the bit line address as a function of the "Y" and "Z" addresses and whether the control gate address is "even" or "odd".
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