| 摘要 |
<p>PROBLEM TO BE SOLVED: To perform high speed operation and to drive a device with low power consumption. SOLUTION: A memory cell 100 has a data holding circuit and four transfer gates 103a, 103b, 104a, and 104b, source terminals or drain terminals of the transfer gates 103a and 103b are connected to a pair of bit lines 105a and 105b to which the memory cell 100 is connected, source terminals or drain terminals of the transfer gates 104a and 104b are connected to a pair of bit lines 115a and 115b connected to a memory cell 110 being adjacent to the memory cell 100 in the row direction.</p> |
