发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
<p>PROBLEM TO BE SOLVED: To accelerate a memory read operation which is constituted using a PLED transistor. SOLUTION: A shunt line L, grounded at both ends and electrically connected to a source power line GND, is inserted in a direction orthogonal to the source power line GND of a MISFET Tr1 and noise (potential) surfacing in the source power line GND is released to the ground potential. By releasing the noise surfacing in the source power line GND to the ground potential, reduction of the voltage between the source and drain of the MISFET Tr1 is suppressed.</p> |
申请公布号 |
JP2003037249(A) |
申请公布日期 |
2003.02.07 |
申请号 |
JP20010221931 |
申请日期 |
2001.07.23 |
申请人 |
HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD |
发明人 |
KUBOTA KISHIYO;HASHIMOTO TAKESHI |
分类号 |
G11C14/00;G11C11/402;G11C16/04;H01L27/10;H01L27/108;(IPC1-7):H01L27/10 |
主分类号 |
G11C14/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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