发明名称 |
INTER MULTIPROCESSOR COMMUNICATION DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To change data volume discretionally at need which can be transferred simultaneously with a fixed range in a FIFO means used for queuing an inter multiprocessor communication. SOLUTION: A capacity setting register 105 to set the number of stages for a FIFO register 104 is arranged inside a circuit to control access 103 to the FIFO register 104 shared for both transmission and reception and capacity distribution of the FIFO register for each processor is performed in accordance with the set point value. And a configuration with more than 3 processors is controlled using a circuit to decide a priority so that a simultaneous access to the FIFO register 104 from a plurality of processors is avoided.
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申请公布号 |
JP2003036240(A) |
申请公布日期 |
2003.02.07 |
申请号 |
JP20010223217 |
申请日期 |
2001.07.24 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
ODAWARA HIDEYUKI |
分类号 |
G06F13/38;G06F5/06;(IPC1-7):G06F13/38 |
主分类号 |
G06F13/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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