| 摘要 |
PROBLEM TO BE SOLVED: To prevent remaining of unetched parts and overetching, even when simultaneously patterning a high concentration region and a low concentration region. SOLUTION: After forming an element isolation oxide film 118, a CMP is conducted with a silicon nitride film 118 as a stopper and the element isolation oxide film 118 is planarized. Thereafter, when the silicon nitride film 118 is removed, a step A' is formed between the peak part of the element isolation oxide film 118 and polysilicon films 106 and 113. Then, when the polysilicon film is deposited further on the polysilicon films 106 and 113, 'drift' of the polysilicon film is generated, and the film becomes thick on the side of a memory cell region and the drift is not generated on a peripheral circuit region. In order to offset the difference in the total thickness of the gate electrode film due to that, the film thickness of the polysilicon film 113 in the peripheral circuit region is formed larger than the film thickness of the polysilicon film 106 in the memory cell region by a prescribed amount.
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