| 摘要 |
PURPOSE: A control gate decoder for a twin MONOS memory provided with 2 bit elimination capability is provided to allow for one or more bit selection within a word line during read and program operations. CONSTITUTION: A control gate decoder for a twin MONOS memory provided with 2 bit elimination capability includes a decoder for control gate lines of a memory array. The control gate lines connected to a plurality of twin MONOS memory cells within the memory array. The decoder containing a plurality of decoder units connected to a plurality of control lines, the plurality of decoder units are divided into a plurality of odd and a plurality of even assigned addresses matching address of the memory cells. The plurality of odd assigned address decoder units connecting a low voltage or an odd assigned voltage to control gate lines with odd assigned addresses. And, the plurality of even assigned address decoder units is connected to the low voltage or an even assigned voltage to control gate lines with even assigned addresses.
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