TIMING GENERATOR AND SEMICONDUCTOR TEST APPARATUS

摘要

A timing generator circuit capable of absorbing a delay time error of a variable delay circuit without increasing the number of bits of path data and suppressing deterioration of the timing accuracy from the designed value to the minimum.The timing generator circuit assigns includes a selection unit 13 for assigning 5−bit delay element candidates to a 3−bit partial bit signal of all the bit signals constituting the path data output from a linearization memory 12,and selecting three delay elements which number is equal to the bit count of the partial bit signal.