发明名称 INTEGRATED CIRCUIT
摘要 A semiconductor chip(10)is provided with decoding circuits(1a−1f)near circuit blocks(2−7)scatteringly disposed.Each of the decoding circuits(1a−1f)is wired with an undecoded signal line(8)comprising an address line and a data line,so that the number of bits of the signal lines(8)may be sufficient for that of wirings to be routed over the semiconductor chip(10).Thus,the total wiring area can be much more reduced than in the conventional case where many decoded signal lines(20)have been routed to respective blocks(2−7).This design purposes to scale down a chip size,reduce crosstalk noise,and facilitate layout.
申请公布号 WO03010818(A1) 申请公布日期 2003.02.06
申请号 WO2002JP06971 申请日期 2002.07.10
申请人 NIIGATA SEIMITSU CO., LTD.;KARASUDANI, MUNEHIRO 发明人 KARASUDANI, MUNEHIRO
分类号 H01L21/822;H01L21/82;H01L23/528;H01L27/02;H01L27/04;(IPC1-7):H01L27/04 主分类号 H01L21/822
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