Semiconductor integrated circuit

摘要

In the first and second regions data not concurrently transferred is transferred by using data lines having the respective different wiring layers. The vertical positions of the data lines are reversed between the first and second regions. In the switching regions the data lines are exchanged between the first and second regions. The parasitic capacitances associated with the two data lines are practically equal to each other so that the delay times of signals transferred along the data lines are equal to each other. This can prevent a circuit malfunction due to a parasitic capacitance difference. In the semiconductor integrated circuit where memory cell arrays and sense amplifier arrays are alternately wired, forming the first and second regions over the memory cell arrays and the switching regions over the sense amplifier arrays makes it easier to exchange the vertical positions of the data lines in the switching regions.