| 摘要 |
A specific address region of a cache address region is set in a non-cache region setting register together with a region setting valid bit in a cache memory. When the specific address region is accessed by a CPU core, access to an external memory is made if a corresponding region is set in a non-cache region by a region setting valid bit. Moreover, an invalidating bit is set to invalidate all cache memory data in the specific address region. In DMA transfer, an inclusion detection circuit detects whether a transfer destination address region is included in the set address region and forcibly sets an invalidating bit according to a result of the detection. A cache system is provided that is capable of setting an address region of a cache object region according to a system architecture with flexibility.
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