发明名称 |
SEMICONDUCTOR MEMORY |
摘要 |
<p>A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq). <IMAGE></p> |
申请公布号 |
EP1282133(A1) |
申请公布日期 |
2003.02.05 |
申请号 |
EP20010912146 |
申请日期 |
2001.03.07 |
申请人 |
NEC CORPORATION |
发明人 |
TAKAHASHI, HIROYUKI;INABA, HIDEO;SONODA, MASATOSHI;KATO, YOSHIYUKI;NAKAGAWA, ATSUSHI |
分类号 |
G11C11/403;G11C11/401;G11C11/406;G11C11/407;G11C11/408;G11C29/04;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/403 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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