Transistor having a high K dielectric and short gate length and method therefor

摘要

A transistor device (19) utilizes a high K dielectric (24) between a gate electrode (16) and a substrate (12). The high K dielectric (24) is etched under the gate electrode (16) so that there is an area between the gate electrode (16) and the substrate (12) that is void of high K dielectric (24). The source/drains extensions (28 and 30) are minimized to extend substantially in alignment with the edge of gate dielectric (24) to reduce overlap with the gate dielectric (24). This results in reduced capacitance between the gate and the source/drain extensions. The void areas (20 and 22) between the gate and the substrate (12) may remain void or may be filled with a low K dielectric, or at least a dielectric that is not high K.