发明名称 Self-adjusting clock phase controlled architecture
摘要 A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.
申请公布号 US6516006(B1) 申请公布日期 2003.02.04
申请号 US19990250161 申请日期 1999.02.16
申请人 MITSUBISHI ELECTRIC AND ELECTRONICS U.S.A., INC. 发明人 WALKER ROBERT M.;CAMACHO STEPHEN M.;ALEXANDER GEORGE W.
分类号 G06F1/10;G06F7/00;H04L7/00;(IPC1-7):H04J3/06 主分类号 G06F1/10
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