发明名称 |
Balanced sense amplifier control for open digit line architecture memory devices |
摘要 |
A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
|
申请公布号 |
US6515925(B2) |
申请公布日期 |
2003.02.04 |
申请号 |
US20010805933 |
申请日期 |
2001.03.15 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
GRAHAM SCOT M.;DERNER SCOTT J.;PORTER STEPHEN R. |
分类号 |
G11C7/06;G11C7/08;G11C11/4091;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|