Circuit structure for providing a hierarchical decoding in semiconductor memory devices

摘要

A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common is presented. The device includes a PMOS first transistor having conduction terminals connected respectively to the main word line and the local word line, an NMOS second transistor having conduction terminals connected respectively to the local word line and the main word line, and a PMOS third transistor having conduction terminals connected respectively to the main word line and the local word line. Such a third transistor is a charge transistor that reduces the charging time for the local word line.