| 摘要 |
The present invention provides a microprocessor capable of improving the throughput of a CPU. Module like the program ROMs in which instruction accesses are concentrated by a CPU are put together in a first Princeton bus, and modules like the external bus I/F, SDRAM I/F, peripheral bus I/F in which data accesses are mainly concentrated are put together in a second Princeton bus. Therefore, the instruction access and the data access can be carried out in parallel with respect to the buses of the instruction bus and the data bus individually through a bus control unit. Because the buses can be used efficiently, the throughput of the CPU can be improved substantially.
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