发明名称 |
Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system |
摘要 |
A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.
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申请公布号 |
US6516442(B1) |
申请公布日期 |
2003.02.04 |
申请号 |
US19990281749 |
申请日期 |
1999.03.30 |
申请人 |
CONEXANT SYSTEMS, INC. |
发明人 |
WANG YUANLONG;BIARD BRIAN R.;FU DANIEL;COHEN EARL T.;AMDAHL CARL G. |
分类号 |
G06C13/00;G06F1/04;G06F3/00;G06F13/00;H03M13/00;H04B1/38;H04B3/20;H04L5/16;(IPC1-7):H03M13/00 |
主分类号 |
G06C13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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