| 摘要 |
A method of testing a CMOS integrated circuit including the steps of applying a test signal to a CMOS integrated circuit under test and measuring a quiescent power supply current at a plurality of strobe points, calculating defect current estimates corresponding to the strobe points based on average value ratios of the quiescent power supply currents at the plurality of strobe points calculated in advance for a good CMOS integrated circuit, measured values of the quiescent power supply current at the plurality of strobe points, and an average value of the measured values of the quiescent power supply currents, and judging the CMOS integrated circuit under test as a defect when an absolute value of a calculated defect current estimate is larger than an absolute value of an allowable error of a measured value of the quiescent power supply current, whereby it is possible to detect the defect current of a CMOS integrated circuit with a large quiescent power supply current and a large variation.
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