SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING SEQUENTIALLY WORD LINES

摘要

PURPOSE: A semiconductor memory device for controlling sequentially word lines is provided to reduce a refresh cycle by activating sequentially plural word lines within one cycle. CONSTITUTION: A semiconductor memory device for controlling sequentially word lines includes a control clock(10), a refresh logic unit(12), a refresh counter(22), a row address buffer(16), and a row decoder(18). The control clock(10) generates a refresh mode signal in response to an external control clock. The refresh logic unit(12) generates an enable signal to perform a refresh operation in response to the refresh mode signal. The refresh counter(22) generates sequentially row address signals of n number during one cycle of an activation period of a row address strobe signal in response to the enable signal. The row address buffer(16) is used for outputting sequentially the row address signals of n number. The row decoder(18) includes word line drivers of 2n number to decode the row address signals of n number during a refresh operation period and enable the word lines selected from each decoding process.