| 摘要 |
PROBLEM TO BE SOLVED: To suppress reduce data processing speed due to erroneous cache by excluding probabilistic elements from behaviors of a cache memory. SOLUTION: A computer 10 is provided with a CPU 11 to carry out a given instruction and main storage memory 16 to be defined as an accessing object of the CPU 11. In addition, the computer 10 is provided with the cache memory 13 to act for write and/or read of data to be performed between the CPU 11 and the main storage memory 16 and a cache memory control part 15 to lock a cache line to write and/or read data by accessing the cache memory 13 by the CPU 11 based on the instruction given to the CPU 11 and to unlock the cache line according to access to an address of the locked cache line by the CPU 11.
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