发明名称 ARITHMETIC PROCESSING UNIT FOR USING MAXIMUM LIKELIHOOD SEQUENCE ESTIMATE METHOD
摘要 PROBLEM TO BE SOLVED: To provide an arithmetic processing unit that applies equalization processing of a maximum likelihood sequence estimate type at a low operating speed to multi-value modulated reception data. SOLUTION: Branch metric generating sections 16 and placed in parallel by 2 to the power of number of bits in one symbol of a received signal and reduce an object symbol of the received signal from a channel estimate value every time an output of a counter 1 is incremented to generate a branch metric. ACS(Add, Compare, Select) arithmetic sections 31 are placed in parallel by 2 to the power of number of bits in one symbol of the received signal to conduct the ACS arithmetic operation on the basis of the path metric read from a storage section 20 and a plurality of branch metrics generated by the branch metric generating sections 16 to calculate a maximum likelihood state and to update a maximum likelihood path metric.
申请公布号 JP2003032153(A) 申请公布日期 2003.01.31
申请号 JP20010218763 申请日期 2001.07.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMANAKA RIYUUTAROU;FUTAKI SADAKI;SAITO YOSHIKO;SUZUKI HIDETOSHI
分类号 H03M13/41;H04B3/06;H04B7/005;H04L27/00;H04L27/01 主分类号 H03M13/41
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