| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce internal memory capacity required for interpolation operation by commonly using a memory for storing forward prediction data and a memory for storing results of bi-directional interpolation operation. SOLUTION: The circuit is provided with, in performing bi-directional interpolation operation, an output control section 33 consisting of a shift register 29 into which forward prediction data are inputted, a counter 24, a decoder for decoding a counter value 25 and a data output control section 31 for controlling a timing of data stored in the register 29 on the basis of a decoding flag 27 from the decoder 26, and an output data storing memory address generator 34 for controlling read/write operation of the data outputted from the section 33 into/from an output data storing memory. This configuration enables the common use of the memory for storing the forward prediction data and the memory for storing the results of bi-directional interpolation operation, and the number of internal memories can be reduced.</p> |
