发明名称 METHOD FOR SETTING WIRING PATH OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To complete detailed wiring intended by a layout designer in a short time in wiring path setting of a semiconductor integrated circuit. SOLUTION: A floor plan and such grid lines that covers the floor plan are displayed after deciding the floor plan of a semiconductor integrated circuit chip, and when unit coordinate areas (grid area) surrounded with adjacent grid lines where an inter-block net being an object passes through and their sequences are instructed, the coordinates values and passing sequences of the grid areas are set as a rough wiring path. Next, automatic detailed wiring is performed under a condition that the object inter-block net passes through the rough wiring path which has been set after deciding detailed arrangement of a gate.
申请公布号 JP2003030266(A) 申请公布日期 2003.01.31
申请号 JP20010211642 申请日期 2001.07.12
申请人 HITACHI LTD 发明人 MUNEMURA TAIZO;SHIGEGAKI MASATO
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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