| 摘要 |
PROBLEM TO BE SOLVED: To suppress a decrease in the surge resistance of an output circuit due to a potential rise of a power source line in an ESD test of a semiconductor integrated circuit device. SOLUTION: The semiconductor integrated circuit device comprises an externally connecting pad 1, an electrostatic discharge protective circuit 2, an output circuit 3, an output prebuffer circuit 4, and an internal circuit 21. The integrated circuit device protects the output circuit 3 against a surge invaded from the pad 1 by the protective circuit 2. The integrated circuit device further comprises a PMIS transistor 25 for fixing a substrate potential in which a gate is connected to the pad 1 and provided between an n-type substrate region (n-well) and a power source line 19. In the case of ESD testing, when a positive charge is applied to the pad 1 since the substrate potential fixing PMIS transistor 25 is turned OFF, the potential rise of the power source line 19 is suppressed.
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